EVAL-AD5443EB【PDF 18/24 页】CAP X7R 470PF 50V 10% 0603

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REV. 0

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AD5426/AD5432/AD5443

MC68HC11 Interface to AD5426/AD5432/AD5443 Interface

Figure 16 shows an example of a serial interface between the

DAC and the MC68HC11 microcontroller. The serial peripheral

interface (SPI) on the MC68HC11 is configured for master

mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock

phase bit (CPHA) = 1. The SPI is configured by writing to the

SPI control register (SPCR)—see the 68HC11 User Manual.

SCK of the 68HC11 drives the SCLK of the DAC interface, the

MOSI output drives the serial data line (D

) of the AD5516.

The

SYNC

signal is derived from a port line (PC7). When data is

being transmitted to the AD5516, the

SYNC

line is taken low

(PC7). Data appearing on the MOSI output is valid on the falling

edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit

bytes with only eight falling clock edges occurring in the transmit

cycle. Data is transmitted MSB first. To load data to the DAC,

PC7 is left low after the first eight bits are transferred, and a second

serial write operation is performed to the DAC. PC7 is taken high

at the end of this procedure.

If the user wants to verify the data previously written to the input

shift register, the SDO line could be connected to MISO of the

MC68HC11, and with

SYNC

low, the shift register would clock

data out on the rising edges of SCLK.

SCLK

SCK

AD5426/

AD5432/

AD5443

SYNC

PC7

SDIN

MOSI

MC68HC11

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 16. 68HC11/68L11 to AD5426/AD5432/AD5443

Interface

MICROWIRE to AD5426/AD5432/AD5443 Interface

Figure 17 shows an interface between the DAC and any

MICROWIRE compatible device. Serial data is shifted out on

the falling edge of the serial clock, SK, and is clocked into the

DAC input shift register on the rising edge of SK, which corre-

sponds to the falling edge of the DACs SCLK.

SCLK

MICROWIRE

SYNC

SDIN

AD5426/

AD5432/

AD5443

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. MICROWIRE to AD5426/AD5432/AD5443

Interface

PIC16C6x/7x to AD5426/AD5432/AD5443

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit (CKP) = 0. This is

done by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In

this example, I/O port RA1 is being used to provide a

SYNC

signal

and to enable the serial port of the DAC. This microcontroller

transfers only eight bits of data during each serial transfer operation;

therefore, two consecutive write operations are required. Figure 18

shows the connection diagram.

SCLK

SCK/RC3

PIC16C6x/7x

SYNC

RA1

SDIN

SDI/RC4

AD5426/

AD5432/

AD5443

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 18. PIC16C6x/7x to AD5426/AD5432/AD5443

Interface

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5426/AD5432/AD5443 is mounted should be designed so

that the analog and digital sections are separated, and confined

to certain areas of the board. If the DAC is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the device.

These DACs should have ample supply bypassing of 10 F in

parallel with 0.1 F on the supply located as close to the pack-

age as possible, ideally right up against the device. The 0.1 F

capacitor should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types that provide a low impedance path to ground at high

frequencies, to handle transient currents due to internal logic

switching. Low ESR 1 F to 10 F tantalum or electrolytic

capacitors should also be applied at the supplies to minimize

transient disturbance and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with

digital ground to avoid radiating noise to other parts of the board,

and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micros-

trip technique is by far the best, but not always possible with a

double-sided board. In this technique, the component side of the

board is dedicated to ground plane while signal traces are placed

on the solder side.

It is good practice to employ compact, minimum lead length

PCB layout design. Leads to the input should be as short as

possible to minimize IR drops and stray inductance.

The PCB metal traces between V

REF

and R

should also be

matched to minimize gain error. To maximize on high frequency

performance, the I-to-V amplifier should be located as close to

the device as possible.

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